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connection diagram 8-pin plastic dip, cerdip and soic out1 ?n1 +in1 v v+ out2 ?n2 +in2 1 2 3 4 8 7 6 5 AD822 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a single supply, rail-to-rail low power fet-input op amp AD822 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features true single supply operation output swings rail to rail input voltage range extends below ground single supply capability from +3 v to +36 v dual supply capability from 6 1.5 v to 6 18 v high load drive capacitive load drive of 350 pf, g = 1 minimum output current of 15 ma excellent ac performance for low power 800 m a max quiescent current per amplifier unity gain bandwidth: 1.8 mhz slew rate of 3.0 v/ m s good dc performance 800 m v max input offset voltage 2 m v/ 8 c typ offset voltage drift 25 pa max input bias current low noise 13 nv/ ? hz @ 10 khz no phase inversion applications battery powered precision instrumentation photodiode preamps active filters 12- to 14-bit data acquisition systems medical instrumentation low power references and regulators product description the AD822 is a dual precision, low power fet input op amp that can operate from a single supply of +3.0 v to 36 v, or dual supplies of 1.5 v to 18 v. it has true single supply capability with an input voltage range extending below the negative rail, allowing the AD822 to accommodate input signals below ground in the single supply mode. output voltage swing extends to within 10 mv of each rail providing the maximum output dynamic range. offset voltage of 800 m v max, offset voltage drift of 2 m v/ c, input bias currents below 25 pa and low input voltage noise provide dc precision with source impedances up to a gigaohm. 1.8 mhz unity gain bandwidth, C93 db thd at 10 khz and 3 v/ m s slew rate are provided with a low supply current of 800 m a per amplifier. the AD822 drives up to 350 pf of direct capacitive load as a follower, and provides a minimum output current of 15 ma. this allows the amplifier to handle a wide range of load conditions. this combination of ac and dc performance, plus the outstanding load drive capability, results in an exceptionally versatile amplifier for the single supply user. the AD822 is available in four performance grades. the a and b grades are rated over the industrial temperature range of C40 c to +85 c. there is also a 3 volt gradethe AD822a-3v, rated over the industrial temperature range. the mil grade is rated over the military temperature range of C55 c to +125 c and is available processed on standard military drawing. the AD822 is offered in three varieties of 8-pin package: plastic dip, hermetic cerdip and surface mount (soic) as well as die form. 10 90 100 0% 1v 1v 20 s 1v 5v v out 0v (gnd) gain of +2 amplifier; v s = +5, 0, v in = 2.5 v sine centered at 1.25 volts, r l = 100 k w input voltage noise vs. frequency 100 10 1 10 100 10k 1k input voltage noise ?nv/ ? hz frequency ?hz
rev. a C2C AD822Cspecifications (v s = 0, 5 volts @ t a = +25 8 c, v cm = 0 v, v out = 0.2 v unless otherwise noted) AD822a AD822b AD822s 1 parameter conditions min typ max min typ max min typ max units dc performance initial offset 0.1 0.8 0.1 0.4 0.1 0.8 mv max offset over temperature 0.5 1.2 0.5 0.9 0.5 mv offset drift 2 2 2 m v/ c input bias current v cm = 0 v to 4 v 2 25 2 10 2 25 pa at t max 0.5 5 0.5 2.5 0.5 na input offset current 2 20 2 10 2 20 pa at t max 0.5 0.5 1.5 na open-loop gain v o = 0.2 v to 4 v r l = 100 k 500 1000 500 1000 500 1000 v/mv t min to t max 400 400 v/mv r l = 10 k 80 150 80 150 80 150 v/mv t min to t max 80 80 v/mv r l = 1 k 15 30 15 30 15 30 v/mv t min to t max 10 10 v/mv noise/harmonic performance input voltage noise 0.1 hz to 10 hz 2 2 2 m v p-p f = 10 hz 25 25 25 nv/ ? hz f = 100 hz 21 21 21 nv/ ? hz f = 1 khz 16 16 16 nv/ ? hz f = 10 khz 13 13 13 nv/ ? hz input current noise 0.1 hz to 10 hz 18 18 18 fa p-p f = 1 khz 0.8 0.8 0.8 fa/ ? hz harmonic distortion r l = 10 k to 2.5 v f = 10 khz v o = 0.25 v to 4.75 v C93 C93 C93 db dynamic performance unity gain frequency 1.8 1.8 1.8 mhz full power response v o p-p = 4.5 v 210 210 210 khz slew rate 3 3 3 v/ m s settling time to 0.1% v o = 0.2 v to 4.5 v 1.4 1.4 1.4 m s to 0.01% 1.8 1.8 1.8 m s matching characteristics initial offset 1.0 0.5 1.6 mv max offset over temperature 1.6 1.3 mv offset drift 3 3 m v/ c input bias current 20 10 20 pa crosstalk @ f = 1 khz r l = 5 k w C130 C130 C130 db f = 100 khz C93 C93 C93 db input characteristics common-mode voltage range 2 C0.2 4 C0.2 4 C0.2 4 v t min to t max C0.2 4 C0.2 4 v cmrr v cm = 0 v to +2 v 66 80 69 80 66 80 db t min to t max 66 66 db input impedance differential 10 13 || 0.5 10 13 || 0.5 10 13 || 0.5 w|| pf common mode 10 13 || 2.8 10 13 || 2.8 10 13 || 2.8 w|| pf output characteristics output saturation voltage 3 v ol Cv ee i sink = 20 m a 575757mv t min to t max 10 10 mv v cc Cv oh i source = 20 m a 1014 1014 1014mv t min to t max 20 20 mv v ol Cv ee i sink = 2 ma 40 55 40 55 40 55 mv t min to t max 80 80 mv v cc Cv oh i source = 2 ma 80 110 80 110 80 110 mv t min to t max 160 160 mv v ol Cv ee i sink = 15 ma 300 500 300 500 300 500 mv t min to t max 1000 1000 mv v cc Cv oh i source = 15 ma 800 1500 800 1500 800 1500 mv t min to t max 1900 1900 mv operating output current 15 15 15 ma t min to t max 12 12 ma capacitive load drive 350 350 350 pf power supply quiescent current t min to t max 1.24 1.6 1.24 1.6 1.24 ma power supply rejection v s + = 5 v to 15 v 70 80 66 80 70 80 db t min to t max 70 66 db
(v s = 6 5 volts @ t a = +25 8 c, v cm = 0 v, v out = 0 v unless otherwise noted) AD822a AD822b AD822s 1 parameter conditions min typ max min typ max min typ max units dc performance initial offset 0.1 0.8 0.1 0.4 0.1 mv max offset over temperature 0.5 1.5 0.5 1 0.5 mv offset drift 2 2 2 m v/ c input bias current v cm = C5 v to 4 v 2 25 2 10 2 25 pa at t max 0.5 5 0.5 2.5 0.5 na input offset current 2 20 2 10 2 pa at t max 0.5 0.5 1.5 na open-loop gain v o = C4 v to 4 v r l = 100 k 400 1000 400 1000 400 1000 v/mv t min to t max 400 400 v/mv r l = 10 k 80 150 80 150 80 150 v/mv t min to t max 80 80 v/mv r l = 1 k 20 30 20 30 20 30 v/mv t min to t max 10 10 v/mv noise/harmonic performance input voltage noise 0.1 hz to 10 hz 2 2 2 m v p-p f = 10 hz 25 25 25 nv/ ? hz f = 100 hz 21 21 21 nv/ ? hz f = 1 khz 16 16 16 nv/ ? hz f = 10 khz 13 13 13 nv/ ? hz input current noise 0.1 hz to 10 hz 18 18 18 fa p-p f = 1 khz 0.8 0.8 0.8 fa/ ? hz harmonic distortion r l = 10 k f = 10 khz v o = 4.5 v C93 C93 C93 db dynamic performance unity gain frequency 1.9 1.9 1.9 mhz full power response v o p-p = 9 v 105 105 105 khz slew rate 3 3 3 v/ m s settling time to 0.1% v o = 0 v to 4.5 v 1.4 1.4 1.4 m s to 0.01% 1.8 1.8 1.8 m s matching characteristics initial offset 1.0 0.5 1.6 mv max offset over temperature 3 2 2 mv offset drift 3 3 m v/ c input bias current 25 10 25 pa crosstalk @ f = 1 khz r l = 5 k w C130 C130 C130 db f = 100 khz C93 C93 C93 db input characteristics common-mode voltage range 2 C5.2 4 C5.2 4 C5.2 4 v t min to t max C5.2 4 C5.2 4 v cmrr v cm = C5 v to +2 v 66 80 69 80 66 80 db t min to t max 66 66 db input impedance differential 10 13 || 0.5 10 13 || 0.5 10 13 || 0.5 w|| pf common mode 10 13 || 2.8 10 13 || 2.8 10 13 || 2.8 w|| pf output characteristics output saturation voltage 3 v ol Cv ee i sink = 20 m a 575757mv t min to t max 10 10 mv v cc Cv oh i source = 20 m a 1014 1014 1014mv t min to t max 20 20 mv v ol Cv ee i sink = 2 ma 40 55 40 55 40 55 mv t min to t max 80 80 mv v cc Cv oh i source = 2 ma 80 110 80 110 80 110 mv t min to t max 160 160 mv v ol Cv ee i sink = 15 ma 300 500 300 500 300 500 mv t min to t max 1000 1000 mv v cc Cv oh i source = 15 ma 800 1500 800 1500 800 1500 mv t min to t max 1900 1900 mv operating output current 15 15 15 ma t min to t max 12 12 ma capacitive load drive 350 350 350 pf power supply quiescent current t min to t max 1.3 1.6 1.3 1.6 1.3 ma power supply rejection v s + = 5 v to 15 v 70 80 66 80 70 80 db t min to t max 70 66 db AD822 rev. a C3C
AD822a AD822b AD822s 1 parameter conditions min typ max min typ max min typ max units dc performance initial offset 0.4 2 0.3 1.5 0.4 2.0 mv max offset over temperature 0.5 3 0.5 2.5 0.5 mv offset drift 2 2 2 m v/ c input bias current v cm = 0 v 2 25 2 12 2 25 pa v cm = C10 v 40 40 40 pa at t max v cm = 0 v 0.5 5 0.5 2.5 0.5 na input offset current 2 20 2 12 2 20 pa at t max 0.5 0.5 1.5 na open-loop gain v o = +10 v to C10 v r l = 100 k 500 2000 500 2000 500 2000 v/mv t min to t max 500 500 v/mv r l = 10 k 100 500 100 500 150 400 v/mv t min to t max 100 100 v/mv r l = 1 k 30 45 30 45 30 45 v/mv t min to t max 20 20 v/mv noise/harmonic performance input voltage noise 0.1 hz to 10 hz 2 2 2 m v p-p f = 10 hz 25 25 25 nv/ ? hz f = 100 hz 21 21 21 nv/ ? hz f = 1 khz 16 16 16 nv/ ? hz f = 10 khz 13 13 13 nv/ ? hz input current noise 0.1 hz to 10 hz 18 18 18 fa p-p f = 1 khz 0.8 0.8 0.8 fa/ ? hz harmonic distortion r l = 10 k f = 10 khz v o = 10 v C85 C85 C85 db dynamic performance unity gain frequency 1.9 1.9 1.9 mhz full power response v o p-p = 20 v 45 45 45 khz slew rate 3 3 3 v/ m s settling time to 0.1% v o = 0 v to 10 v 4.1 4.1 4.1 m s to 0.01% 4.5 4.5 4.5 m s matching characteristics initial offset 3 2 0.8 mv max offset over temperature 4 2.5 1.0 mv offset drift 3 3 m v/ c input bias current 25 12 25 pa crosstalk @ f = 1 khz r l = 5 k w C130 C130 C130 db f = 100 khz C93 C93 C93 db input characteristics common-mode voltage range 2 C15.2 14 C15.2 14 C15.2 14 v t min to t max C15.2 14 C15.2 14 v cmrr v cm = C15 v to 12 v 70 80 74 90 70 90 db t min to t max 70 74 db input impedance differential 10 13 || 0.5 10 13 || 0.5 10 13 || 0.5 w|| pf common mode 10 13 || 2.8 10 13 || 2.8 10 13 || 2.8 w|| pf output characteristics output saturation voltage 3 v ol Cv ee i sink = 20 m a 575757mv t min to t max 10 10 mv v cc Cv oh i source = 20 m a 1014 1014 1014mv t min to t max 20 20 mv v ol Cv ee i sink = 2 ma 40 55 40 55 40 55 mv t min to t max 80 80 mv v cc Cv oh i source = 2 ma 80 110 80 110 80 110 mv t min to t max 160 160 mv v ol Cv ee i sink = 15 ma 300 500 300 500 300 500 mv t min to t max 1000 1000 mv v cc Cv oh i source = 15 ma 800 1500 800 1500 800 1500 mv t min to t max 1900 1900 mv operating output current 20 20 20 ma t min to t max 15 15 ma capacitive load drive 350 350 350 pf power supply quiescent current t min to t max 1.4 1.8 1.4 1.8 1.4 ma power supply rejection v s + = 5 v to 15 v 70 80 70 80 70 80 db t min to t max 70 70 db AD822Cspecifications (v s = 6 15 volts @ t a = +25 8 c, v cm = 0 v, v out = 0 v unless otherwise noted) rev. a C4C
AD822 rev. a C5C (v s = 0, 3 volts @ t a = +25 8 c, v cm = 0 v, v out = 0.2 v unless otherwise noted) AD822a-3 v parameter conditions min typ max units dc performance initial offset 0.2 1 mv max offset over temperature 0.5 1.5 mv offset drift 1 m v/ c input bias current v cm = 0 v to +2 v 2 25 pa at t max 0.5 5 na input offset current 220 pa at t max 0.5 na open-loop gain v o = 0.2 v to 2 v r l = 100 k 300 1000 v/mv t min to t max 300 v/mv r l = 10 k 60 150 v/mv t min to t max 60 v/mv r l = 1 k 10 30 v/mv t min to t max 8 v/mv noise/harmonic performance input voltage noise 0.1 hz to 10 hz 2 m v p-p f = 10 hz 25 nv/ ? hz f = 100 hz 21 nv/ ? hz f = 1 khz 16 nv/ ? hz f = 10 khz 13 nv/ ? hz input current noise 0.1 hz to 10 hz 18 fa p-p f = 1 khz 0.8 fa/ ? hz harmonic distortion r l = 10 k to 1.5 v f = 10 khz v o = 1.25 v C92 db dynamic performance unity gain frequency 1.5 mhz full power response v o p-p = 2.5 v 240 khz slew rate 3v/ m s settling time to 0.1% v o = 0.2 v to 2.5 v 1 m s to 0.01% 1.4 m s matching characteristics initial offset 1mv max offset over temperature 2mv offset drift 2 m v/ c input bias current 10 pa crosstalk @ f = 1 khz r l = 5 k w C130 db f = 100 khz C93 db input characteristics common-mode voltage range 2 C0.2 2 v t min to t max C0.2 2 v cmrr v cm = 0 v to +1 v 60 74 db t min to t max 60 db input impedance differential 10 13 || 0.5 w|| pf common mode 10 13 || 2.8 w|| pf output characteristics output saturation voltage 3 v ol Cv ee i sink = 20 m a57mv t min to t max 10 mv v cc Cv oh i source = 20 m a1014mv t min to t max 20 mv v ol Cv ee i sink = 2 ma 40 55 mv t min to t max 80 mv v cc Cv oh i source = 2 ma 80 110 mv t min to t max 160 mv v ol Cv ee i sink = 10 ma 200 400 mv t min to t max 400 mv v cc Cv oh i source = 10 ma 500 1000 mv t min to t max 1000 mv operating output current 15 ma t min to t max 12 ma capacitive load drive 350 pf power supply quiescent current t min to t max 1.24 1.6 ma power supply rejection v s + = 3 v to 15 v 70 80 db t min to t max 70 db
C6C AD822 rev. a notes 1 see standard military drawing for 883b specifications. 2 this is a functional specification. amplifier bandwidth decreases when the input common-mode voltage is driven in the range (+v s C 1 v) to +v s . common-mode error voltage is typically less than 5 mv with the common-mode voltage set at 1 volt below the positive supply. 3 v ol Cv ee is defined as the difference between the lowest possible output voltage (v ol ) and the minus voltage supply rail (v ee ). v cc Cv oh is defined as the difference between the highest possible output voltage (v oh ) and the positive supply voltage (v cc ). specifications subject to change without notice. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD822 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation plastic dip (n) . . . . . . . . . . . . . . observe derating curves cerdip (q) . . . . . . . . . . . . . . . . . . observe derating curves soic (r) . . . . . . . . . . . . . . . . . . . observe derating curves input voltage . . . . . . . . . . . . . . (+v s + 0.2 v) to C(20 v + v s ) output short circuit duration . . . . . . . . . . . . . . . . indefinite differential input voltage . . . . . . . . . . . . . . . . . . . . . . . 30 v storage temperature range (n) . . . . . . . . . C65 c to +125 c storage temperature range (q) . . . . . . . . . C65 c to +150 c storage temperature range (r) . . . . . . . . . C65 c to +150 c operating temperature range AD822a/b . . . . . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c AD822s . . . . . . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c lead temperature range (soldering 60 sec) . . . . . . . +260 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 8-pin plastic dip package: q ja = 90 c/watt 8-pin cerdip package: q ja = 110 c/watt 8-pin soic package: q ja = 160 c/watt maximum power dissipation the m aximum power that can be safely dissipated by the AD822 is limited by the associated rise in junction temperature. for plastic packages, the maximum safe junction temperature is 145 c. for the cerdip packages, the maximum junction temperature is 175 c. if these maximums are exceeded momentarily, proper circuit operation will be restored as soon as the die temperature is reduced. leaving the device in the overheated condition for an extended period can result in device burnout. to ensure proper operation, it is important to observe the derating curves shown in figure 24. while the AD822 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature is not exceeded under all conditions. with power supplies 12 volts (or less) at an ambient temperature of +25 c or less, if the output node is shorted to a supply rail, then the amplifier will not be destroyed, even if this condition persists for an extended period. ordering guide temperature package package m odel 1 range description option AD822an C40 c to +85 c 8-pin plastic n-8 mini-dip AD822bn C40 c to +85 c 8-pin plastic n-8 mini-dip AD822ar C40 c to +85 c 8-pin soic r-8 AD822br C40 c to +85 c 8-pin soic r-8 AD822ar-3v C40 c to +85 c 8-pin soic r-8 AD822an-3v C40 c to +85 c 8-pin plastic n-8 mini-dip AD822a chips C40 c to +85 cdie standard military drawing 2 C55 c to +125 c 8-pin cerdip q-8 notes 1 spice model is available on adi model disc. 2 contact factory for availability. metalization photograph contact factory for latest dimensions. dimensions shown in inches and (mm). AD822Cspecifications
0.5 50 0 0 30 10 ?.4 20 ?.5 40 0.4 0.3 0.2 0.1 ?.1 ?.2 ?.3 offset voltage ?mv number of units v s = 0v, 5v 60 70 figure 1. typical distribution of offset voltage (390 units) offset voltage drift ? m v/ c % in bin 16 0 10 4 2 ?0 ?2 8 6 10 12 14 8 6 4 2 0 ? ? ? ? v s = 5v v s = 15v figure 2. typical distribution of offset voltage drift (100 units) 50 0 10 15 5 1 10 0 30 20 25 35 40 45 9 8 7 6 5 4 3 2 input bias current ?pa number of units figure 3. typical distribution of input bias current (213 units) typical characteristicsCAD822 rev. a C7C input bias current ?pa 5 0 ? ? ? 5 4 3 2 1 0 ? ? ? common-mode voltage ?v v s = 5v v s = 0v, +5v and 5v figure 4. input bias current vs. common-mode voltage; v s = +5 v, 0 v and v s = 5v input bias current ?pa common-mode voltage ?v 1k 10 0.1 ?6 ?2 16 12 8 4 0 ? ? 100 1 figure 5. input bias current vs. common-mode voltage; v s = 15 v 100k 100 0.1 20 40 140 120 100 80 60 1k 10k 1 10 temperature ? c input bias current ?pa figure 6. input bias current vs. temperature; v s = 5 v, v cm = 0
10m 100k 10k 100 1k 100k 10k 1m load resistance w open-loop gain ?v/v v s = 15v v s = 0v, 5v v s = 0v, 3v figure 7. open-loop gain vs. load resistance 140 10m 100k 10k 1m ?0 ?0 120 100 80 60 40 20 0 ?0 temperature ? c open-loop gain ?v/v v s = 15v v s = 0v, 5v v s = 15v v s = 0v, 5v v s = 15v v s = 0v, 5v r l = 100k w r l = 10k w r l = 600 w figure 8. open-loop gain vs. temperature 300 ?00 16 0 ?00 ?2 ?00 ?6 200 100 12 4 0 ? 8 ? output voltage ?v input voltage ? m v r l = 100k w r l = 10k w r l = 600 w figure 9. input error voltage vs. output voltage for resistive loads AD822Ctypical characteristics rev. a C8C 40 ?0 0 300 20 ?0 60 0 180 240 120 pos rail output voltage from supply rails mv input voltage ? m v r l = 2k w r l = 20k w r l = 100k w pos rail neg rail neg rail neg rail pos rail figure 10. input error voltage with output voltage within 300 mv of either supply rail for various resistive loads; v s = 5v 1k 100 1 10 10k 1k 100 1 frequency ?hz 10 input voltage noise ?nv/ ? hz figure 11. input voltage noise vs. frequency ?0 ?0 ?10 100 1k 100k 10k ?0 ?00 ?0 ?0 ?0 frequency ?hz thd ?db r l = 10k w a cl = ? v s = 15v; v out = 20v p-p v s = 5v; v out = 9v p-p v s = 0v, 5v; v out = 4.5v p-p v s = 0v, 3v; v out = 2.5v p-p figure 12. total harmonic distortion vs. frequency
AD822 rev. a C9C 50 0 10 100 10m 1m 100k 10k 1k 60 70 80 90 10 20 30 40 frequency ?hz common-mode rejection ?db v s = 15v v s = 0v, 5v v s = 0v, 3v figure 16. common-mode rejection vs. frequency ?5 c common-mode voltage from supply rails ?volts common-mode error voltage ?mv 5 0 3 3 1 2 ? 4 2 1 0 negative rail positive rail ?5 c +125 c +25 c +125 c figure 17. absolute common-mode error vs. common- mode voltage from supply rails (v s C v cm ) 1000 100 0 0.001 0.01 100 10 1 0.1 10 load current ?ma output saturation voltage ?mv v s v oh v ol v s figure 18. output saturation voltage vs. load current 100 40 ?0 10 100 10m 1m 100k 10k 1k 60 80 0 20 frequency ?hz open-loop gain ?db r l = 2k w c l = 100pf 100 40 ?0 60 80 0 20 phase margin in degrees gain phase figure 13. open-loop gain and phase margin vs. frequency 1k 100 0.01 100 1k 10m 1m 100k 10k 10 1 0.1 frequency ?hz output impedance ? w a cl = +1 v s = 15v figure 14. output impedance vs. frequency +16 ?6 5.0 ? ?2 1.0 0.0 0 ? +4 +8 +12 4.0 3.0 2.0 settling time ? m s output swing from 0 to volts 1% 1% 0.01% 0.1% error figure 15. output swing and error vs. settling time
1000 100 1 ?0 ?0 140 120 100 80 60 40 20 0 ?0 10 temperature ? c output saturation voltage ?mv i source = 10ma i sink = 10ma i source = 1ma i sink = 1ma i source = 10 m a i sink = 10 m a figure 19. output saturation voltage vs. temperature temperature ? c short circuit current limit ?ma 80 0 140 20 10 ?0 ?0 40 30 50 60 70 120 100 80 60 40 20 0 ?0 v s = 15v v s = 15v v s = 0v, 5v v s = 0v, 3v v s = 0v, 5v v s = 0v, 3v ?ut + + + figure 20. short circuit current limit vs. temperature total supply voltage ?volts quiescent current m a 1600 0 36 400 200 4 0 800 600 1000 1200 1400 30 28 24 20 16 12 8 t = +125 c t = +25 c t = ?5 c figure 21. quiescent current vs. supply voltage vs. temperature frequency ?hz power supply rejection ?db 60 0 10 100 10m 1m 100k 10k 1k 30 90 80 20 50 70 10 40 100 ?srr +psrr figure 22. power supply rejection vs. frequency frequency ?hz output voltage ?v 30 15 0 10k 100k 10m 1m 10 5 20 25 v s = 15v v s = 0v, 5v v s = 0v ,3v rl = 2k figure 23. large signal frequency response 2.4 0.4 1.0 0.6 ?0 0.8 ?0 1.6 1.2 1.4 1.8 2.0 2.2 140 120 100 80 60 40 0 ?0 total power dissipation ?w atts 20 ambient temperature ? c 8-pin cerdip (hermetic) 8-pin mini-dip (plastic) 8-pin soic (plastic) (plastic) t jmax = 145 c (hermetic) t jmax = 175 c figure 24. maximum power dissipation vs. temperature for plastic and hermetic packages AD822Ctypical characteristics rev. a C10C
AD822 rev. a C11C frequency ?hz crosstalk ?db ?0 ?40 1m ?10 ?30 1k ?20 300 ?0 ?00 ?0 300k 100k 30k 10k 3k figure 25. crosstalk vs. frequency ? s +v s v in r l 100pf v out 4 0.01 m f 0.01 m f 1/2 AD822 8 figure 26. unity-gain follower 10 90 100 0% 10 m s 5v figure 27. 20 v p-p, 25 khz sine wave input; unity gain follower; r l = 600 w , v s = 15 v +v s 2 3 8 1 0.1 m f 1/2 AD822 1 m f 20v p-p v in 1/2 AD822 5k w 5k w 6 5 7 20k w v out 2.2k w 0.1 m f1 m f ? s crosstalk = 20 log v out 10v in figure 28. crosstalk test circuit 10 90 100 0% 5? 5v figure 29. large signal response unity gain follower; v s = 15 v, r l = 10 k w 10 90 100 0% 500ns 10mv figure 30. small signal response unity gain follower; v s = 15 v, r l = 10 k w
C12C AD822 rev. a 10 90 100 0% 2? 1v gnd figure 31. v s = +5 v, 0 v; unity gain follower response to 0 v to 4 v step +v s v in r l 100pf v out 8 4 0.01 m f 1/2 AD822 figure 32. unity gain follower 10k 20k +v s v in r l 100pf v out 8 4 0.01 m f 1/2 AD822 figure 33. gain of two inverter 10 90 100 0% 2? 1v gnd figure 34. v s = +5 v, 0 v; unity gain follower response to 0 v to 5 v step 10 90 100 0% 2? 10mv gnd figure 35. v s = +5 v, 0 v; unity gain follower response, to 40 mv step centered 40 mv above ground, r l = 10 k w 10 90 100 0% 2? 10mv gnd figure 36. v s = +5 v, 0 v; gain of two inverter response to 20 mv step, centered 20 mv below ground, r l = 10 k w
AD822 rev. a C13C 10 90 100 0% 1v gnd 2? figure 37. v s = +5 v, 0 v; gain of two inverter response to 2.5 v step centered C1.25 v below ground, r l = 10 k w 10 90 100 0% 10? 500mv gnd figure 38. v s = 3 v, 0 v; gain of two inverter, v in = 1.25 v, 25 khz, sine wave centered at C0.75 v, r l = 600 w 90 100 10 0% 1v 1v 2? 10 90 100 0% 1v 1v 10? 1v +v s gnd gnd +5v v in r p v out figure 39. (a) response with r p = 0; v in from 0 to +v s (b) v in = 0 to +v s + 200 mv v out = 0 to +v s r p = 49.9 k w application notes input characteristics in the AD822, n-channel jfets are used to provide a low offset, low noise, high impedance input stage. minimum input common-mode voltage extends from 0.2 v below Cv s to 1 v less than +v s . driving the input voltage closer to the positive rail will cause a loss of amplifier bandwidth (as can be seen by comparing the large signal responses shown in figures 31 and 34) and increased common-mode voltage error as illustrated in figure 17. the AD822 does not exhibit phase reversal for input voltages up to and including +v s . figure 39a shows the response of an AD822 voltage follower to a 0 v to +5 v (+v s ) square wave input. the input and output arc superimposed. the output tracks the input up to +v s without phase reversal. the reduced bandwidth above a 4 v input causes the rounding of the output wave form. for input voltages greater than +v s , a resistor in series with the AD822s noninverting input will prevent phase reversal, at the expense of greater input voltage noise. this is illustrated in figure 39b. since the input stage uses n-channel jfets, input current during normal operation is negative; the current flows out from the input terminals. if the input voltage is driven more positive than +v s C 0.4 v, the input current will reverse direction as internal device junctions become forward biased. this is illustrated in figure 4. a current limiting resistor should be used in series with the input of the AD822 if there is a possibility of the input voltage exceeding the positive supply by more than 300 mv, or if an input voltage will be applied to the AD822 when v s = 0. the amplifier will be damaged if left in that condition for more than 10 seconds. a 1 k w resistor allows the amplifier to withstand up to 10 volts of continuous overvoltage, and increases the input voltage noise by a negligible amount. input voltages less than Cv s are a completely different story. the amplifier can safely withstand input voltages 20 volts below the minus supply voltage as long as the total voltage from the positive supply to the input terminal is less than 36 volts. in addition, the input stage typically maintains picoamp level input currents across that input voltage range. a b.
C14C AD822 rev. a the AD822 is designed for 13 nv/ ? hz wideband input voltage noise and maintains low noise performance to low frequencies (refer to figure 11). this noise performance, along with the AD822s low input current and current noise means that the AD822 contributes negligible noise for applications with source resistances greater than 10 k w and signal bandwidths greater than 1 khz. this is illustrated in figure 40. 100k 0.1 10g 100 1 100k 10 10k 10k 1k 1g 100m 10m 1m source impedance ? w input voltage noise ? m v rms whenever johnson noise is greater than amplifier noise, amplifier noise can be considered negligible for application. resistor johnson noise amplifier generated noise 1khz 10hz figure 40. total noise vs. source impedance output characteristics the AD822 s unique bipolar rail-to-rail output stage swings within 5 mv of the minus supply and 10 mv of the positive supply with no external resistive load. the AD822s approximate output saturation resistance is 40 w sourcing and 20 w sinking. this can be used to estimate output saturation voltage when driving heavier current loads. for instance, when sourcing 5 ma, the saturation voltage to the positive supply rail will be 200 mv, when sinking 5 ma, the saturation voltage to the minus rail will be 100 mv. the amplifiers open-loop gain characteristic will change as a function of resistive load, as shown in figures 7 through 10. for load resistances over 20 k w , the AD822s input error voltage is virtually unchanged until the output voltage is driven to 180 mv of either supply. if the AD822s output is overdriven so as to saturate either of the output devices, the amplifier will recover within 2 m s of its input returning to the amplifiers linear operating region. direct capacitive loads will interact with the amplifiers effective output impedance to form an additional pole in the amplifiers feedback loop, which can cause excessive peaking on the pulse response or loss of stability. worst case is when the amplifier is used as a unity gain follower. figure 41 shows the AD822s pulse response as a unity gain follower driving 350 pf. this amount of overshoot indicates approximately 20 degrees of phase marginthe system is stable, but is nearing the edge. configurations with less loop gain, and as a result less loop bandwidth, will be much less sensitive to capacitance load effects. figure 42 is a plot of capacitive load that will result in a 20 degree phase margin versus noise gain for the AD822. noise gain is the inverse of the feedback attenuation factor provided by the feedback network in use. 10 0% 20mv 2 m s 90 100 figure 41. small signal response of AD822 as unity gain follower driving 350 pf capacitive load 5 1 300 30k 4 2 1k 3 3k 10k capacitive load for 20 phase margin ?pf noise gain ?1+ r f r i r f r i c l figure 42. capacitive load tolerance vs. noise gain figure 43 shows a method for extending capacitance load drive capability for a unity gain follower. with these component values, the circuit will drive 5,000 pf with a 10% overshoot. 8 4 0.01 m f 20pf 20k w 100 w v out v in +v s ? s 0.01 m f c l 1/2 AD822 figure 43. extending unity gain follower capacitive load capability beyond 350 pf
AD822 rev. a C15C applications single supply voltage-to-frequency converter the circuit shown in figure 44 uses the AD822 to drive a low power timer, which produces a stable pulse of width t 1 . the positive going output pulse is integrated by r1-c1 and used as one input to the AD822, which is connected as a differential integrator. the other input (nonloading) is the unknown voltage, v in . the AD822 output drives the timer trigger input, closing the overall feedback loop. 2 6 5 3 4 +10v 0.1 m f c5 r scale ** 10k r1 499k, 1% v in r2 499k, 1% 0v to 2.5v full scale c1 0.01 m f, 2% c2 0.01 m f, 2% u4 ref-02 u1 43 u3b 21 u3a c6 390pf 5% c3 0.1 m f thr tr dis rv+ out cv gnd 48 6 2 7 1 3 5 (npo) c4 0.01 m f r3 * 116k u2 cmos 555 out2 out1 notes: f out = v in /(vref*t 1 ), t 1 = 1.1*r3*c6 * = 1% metal film, <50ppm/ c tc ** = 10%, 20t film, <100ppm/ c tc t 1 = 33 m s for f out = 20khz @ v in = 2.0v = 25khz f s as shown. v ref = 5v cmos 74hco4 1/2 AD822b figure 44. single supply voltage-to-frequency converter typical AD822 bias currents of 2 pa allow megaohm-range source impedances with negligible dc errors. linearity errors on the order of 0.01% full scale can be achieved with this circuit. this performance is obtained with a 5 volt single supply which delivers less than 1 ma to the entire circuit. single supply programmable gain instrumentation ampli fier the AD822 can be configured as a single supply instrumenta- tion amplifier that is able to operate from single supplies down to 3 v, or dual supplies up to 15 v. using only one AD822 rather than three separate op amps, this circuit is cost and power effic ient. AD822 fet inputs 2 pa bias currents minimize offset errors caused by high unbalanced source impedances. an array of precision thin-film resistors sets the in amp gain to be either 10 or 100. these resistors are laser-trimmed to ratio match to 0.01%, and have a maximum differential tc of 5 ppm/ c. table i. AD822 in amp performance parameters v s = 3 v, 0 v v s = 6 5 v cmrr 74 db 80 db common-mode voltage range C0.2 v to +2 v C5.2 v to +4 v 3 db bw, g = 10 180 khz 180 khz g = 100 18 khz 18 khz t settling 2 v step (v s = 0 v, 3 v) 2 m s 5 v (v s = 5 v) 5 m s noise @ f = 1 khz, g = 10 270 nv/ ? hz 270 nv/ ? hz g = 100 2.2 m v/ ? hz 2.2 m v/ ? hz i supply (total) 1.10 ma 1.15 ma 10 90 100 0% 5 m s 1v figure 45a. pulse response of in amp to a 500 mv p-p input signal; v s = +5 v, 0 v; gain = 10 (g =10) v out = (v in1 ? in2 ) (1+ ) +v ref r6 r4 + r5 (g =100) v out = (v in1 ? in2 ) (1+ ) +v ref for r1 = r6, r2 = r5, and r3 = r4 r5 + r6 r4 r1 r2 r3 r4 r5 r6 90k 9k 1k 1k 9k 90k v out v in1 0.1 m f 8 1/2 AD822 1/2 AD822 v in2 r p 1k w 1 2 3 6 5 4 7 ohmtek part # 1043 v ref g =10 g =100 r p 1k w g =100 g =10 +v s figure 45b. a single supply programmable instrumentation amplifier
C16C AD822 rev. a mylar 1f 1/2 AD822 l r headphones 32 w impedance 4.99k mylar 1f 4.99k 1/2 AD822 10k 10k 47.5k 95.3k 47.5k 500f 500f 1 1 3 +3v 2 4 7 5 6 95.3k 8 0.1f 0.1f channel 1 channel 2 low dropout bipolar bridge driver the AD822 can be used for driving a 350 ohm wheatstone bridge. figure 47 shows one half of the AD822 being used to buffer the ad589?a 1.235 v low power reference. the output of +4.5 v can be used to drive an a/d converter front end. the other half of the AD822 is configured as a unity-gain inverter, and generates the other bridge input of e4.5 v. resistors r1 and r2 provide a constant current for bridge excitation. the ad620 low power instrumentation amplifier is used to condition the differential output voltage of the bridge. the gain of the ad620 is programmed using an external resistor r g , and determined by: g = 49.4 k w r g + 1 350 w 350 w 350 w 350 w v ref ev s +v s ad620 4 2 6 5 7 3 r g r2 20 w e4.5v 10k 10k 10k 26.4k, 1% r1 20 w to a/d converter reference input ad589 49.9k +1.235v 0.1f 1f +5v 1f gnd 1% 1% 1% 1/2 AD822 1 1 3 2 8 1/2 AD822 4 7 6 5 +v s +v s +v s ev s 0.1f e5v figure 47. low dropout bipolar bridge driver figure 46. 3 volt single supply stereo headphone driver 3 volt, single supply stereo headphone driver the AD822 exhibits good current drive and thd+n perfor- mance, even at 3 v single supplies. at 1 khz, total harmonic distortion plus noise (thd+n) equals C62 db (0.079%) for a 300 mv p-p output signal. this is comparable to other single supply op amps which consume more power and cannot run on 3 v power supplies. in figure 46, each channel s input signal is coupled via a 1 m f mylar capacitor. resistor dividers set the dc voltage at the non- inverting inputs so that the output voltage is midway between the power supplies (+1.5 v). the gain is 1.5. each half of the AD822 can then be used to drive a headphone channel. a 5 hz high-pass fil ter is realized by the 500 m f capacitors and the head- phones, which can be modeled as 32 ohm load resistors to ground. this ensures that all signals in the audio frequency range (20 hze20 khz) are delivered to the headphones. c1821aC10C9/94 printed in u.s.a. cerdip (q) package 0.005 (0.13) min 0.055 (1.35) max 0.405 (10.29) max 0.150 (3.81) min 0.200 (5.08) max 0.070 (1.78) 0.030 (0.76) 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) bsc seating plane 0.060 (1.52) 0.015 (0.38) 4 1 5 8 0.310 (7.87) 0.220 (5.59) 0.320 (8.13) 0.290 (7.37) 0 -15 0.015 (0.38) 0.008 (0.20) soic (r) package 0.019 (0.48) 0.014 (0.36) 0.050 (1.27) bsc 0.102 (2.59) 0.094 (2.39) 0.197 (5.01) 0.189 (4.80) 0.010 (0.25) 0.004 (0.10) 0.098 (0.2482) 0.075 (0.1905) 0.190 (4.82) 0.170 (4.32) 0.030 (0.76) 0.018 (0.46) 10 0 0.090 (2.29) 8 0 0.020 (0.051) x 45 chamf 1 8 5 4 pin 1 0.157 (3.99 ) 0.150 (3.81 ) 0.244 (6.20) 0.228 (5.79) 0.150 (3.81) mini-dip (n) package 0.011 0.003 (0.28 0.08) 0.30 (7.62) ref 15 0 pin 1 4 5 8 1 0.25 (6.35) 0.31 (7.87) 0.10 (2.54) bsc seating plane 0.035 0.01 (0.89 0.25) 0.18 0.03 (4.57 0.76) 0.033 (0.84) nom 0.018 0.003 (0.46 0.08) 0.125 (3.18) min 0.165 0.01 (4.19 0.25) 0.39 (9.91) max outline dimensions dimensions shown in inches and (mm).

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